1. Field
This document relates to a method for recovering pixel clocks based on an iDP (Internal Display Port) interface and a display device using the same.
2. Related Art
A liquid crystal display has increasingly widened its application range due to the characteristics such as light weight, thin profile, and low power consumption driving. The liquid crystal display is used as a portable computer such as a notebook PC, an office automation device, an audio/video device, an indoor and outdoor advertisement display device, or the like. The liquid crystal display controls electric fields applied to liquid crystal cells so as to modulate light provided from a backlight unit, thereby displaying images.
In order to satisfy needs for high definition display performance from users, the liquid crystal display has increasingly implemented high image quality images at high channel transmission bandwidth and high frame refresh rate for video data. At present, in a television set system, video data transmission between a system on chip (“SoC”) generating video data to be displayed on a liquid crystal display panel and a timing controller controlling operation timings of driving circuits of the liquid crystal display panel uses an LVDS (Low Voltage Differential Signaling) interface. The LVDS interface is advantageous in that it has low power consumption and is less influenced by external noise due to use of low voltage swing level and differential signal pair, but is inappropriate for transmission of video data of high resolution due to the limitation of the data transmission rate.
FIG. 1 is a diagram illustrating an example where a SoC board 6 and a panel control board 4 are connected to each other via an LVDS interface in the related art.
Referring to FIG. 1, the four-port LVDS interface, which transmits video data of 30 bpp (bit per pixel) at a frame refresh rate of 120 Hz and a resolution of FHD (Full High-Definition) 1920×1800, connects the SoC board 6 to the panel control board 4 via a two-port connector and cable 8a and a two-port connector and cable 8b different therefrom. A SoC including an LVDS transmission circuit is mounted on the SoC board 6, and a timing controller 2 including an LVDS reception circuit is mounted on the panel control board 4. The timing controller 2 transmits video data to source drive ICs (Integrated Circuits) via a mini LVDS interface.
Pixel clocks which are necessary to transmit video data of FHD 30 bpp at the frame refresh rate of 120 Hz are transmitted from the SoC to the timing controller 2 in a form of differential signal pairs on the LVDS specification. The frequency of the pixel clocks PXLCLK is given by Equation 1.PXLCLK=(HA+HB)×(VA+VB)×f  (1)
Here, HA represents horizontal active and indicates the number of pixel data to be displayed on one horizontal line of a display panel. HB represents horizontal blank and indicates a value obtained by converting a period where there is no pixel data between neighboring HAs into the number of pixels. VA represents vertical active and indicates the number of pixel data to be displayed on one vertical line of the display panel. VB represents vertical blank and indicates a value obtained by converting a period where there is no pixel data between neighboring VAs into the number of pixels. In addition, f indicates a frame refresh rate.
HB and VB of FHD 120 Hz are respectively 280 and 45 when the frequency of the pixel clocks is 297 MHz. If the frequency of the pixel clocks PXLCLK is calculated using Equation 1, the frequency of the pixel clocks PXLCLK necessary to transmit video data of FHD resolution is 297 MHz. The LVDS interface has a low transmission rate, thus video data is transmitted in parallel using four ports at the rate of 74.25 MHz. A single LVDS port includes six differential signal pairs at 30 bpp, and five pairs are used to transmit video data and the remaining one pair is used to transmit the pixel clocks PXLCLK. The minimum number of pairs required to transmit video data of 30 bpp at the frame refresh rate of 120 Hz is 24, and the number of lines is 48 which is twice thereof. Since the pixel clock dedicated lines exist, four pairs of clock transmission lines are further necessary. Therefore, considering the low transmission rate of the LVDS, the number of lines necessary to transmit video data and pixel clocks increases in geometric progression as the resolution of the display panel becomes high.
A large number of transmission lines applied to the LVDS interface has direct influence on manufacturing costs for display devices, reduces a degree of freedom regarding design of layout of a PCB (Printed Circuit Board), and increases EMI (Electro Magnetic Interference). In addition, EMI on a PCB increases since high frequency clock signals are directly supplied to the PCB. In contrast, the LVDS interface is advantageous in that since the pixel clocks PXLCLK are directly transmitted to a reception circuit Rx from a transmission circuit Tx, the reception circuit Rx need not recover the pixel clocks PXLCLK. Therefore, the LVDS interface can transmit continuous pixel clocks according to all resolutions by applying a defined HB value and a defined VB value without using a data rate throttling (“DRT”) function, if video data is transmitted from the transmission circuit Tx at a frequency of desired pixel clocks PXLCLK as shown in Equation 2 and FIG. 2 and the reception circuit Rx is designed to allow the frequency.BW=PXLCLK×CD  (2)
Here, BW indicates a channel transmission bandwidth of data, and CD indicates color depth.
The iDP interface, which has been developed as a countermeasure for the existing LVDS interface, supports the serial data link rate of 3.24 Gbps for the lanes, and thus it is possible to transmit video data of high color depth, resolution, and frame refresh rate at a low lane count. The iDP interface does not use clock transmission lines separately in the same manner as the DP interface, and thereby it is necessary for the reception circuit Rx to perform a CDR (Clock and Data Recovery) process for recovering clock signals. For this, the iDP interface recovers the pixel clocks in the reception circuit Rx using a 8-bit M/N PLL (Phase Locked Loop) which multiplies received clocks by M/N. Here, N is set to 48, and M is a positive integer. However, it is difficult to apply the iDP interface since a systematic method for recovering the pixel clocks in the reception circuit Rx is not established.